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DATA SHEET
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* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4029B MSI Synchronous up/down counter, binary/decade counter
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parallel data inputs (P0 to P3), four parallel buffered outputs (O0 to O3) and an active LOW terminal count output (TC).
HEF4029B MSI
Information on P0 to P3 is asynchronously loaded into the counter while PL is HIGH, independent of CP. The counter is advanced one count on the LOW to HIGH transition of CP when CE and PL are LOW. The TC signal is normally HIGH and goes LOW when the counter reaches its maximum count in the UP mode, or the minimum count in the DOWN mode provided CE is LOW.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING HEF4029BP(N): HEF4029BD(F): HEF4029BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PL P0 to P3 BIN/DEC UP/DN CE CP O0 to O3 TC parallel load input parallel data inputs binary/decade control input up/down control input count enable input (active LOW) clock input (LOW to HIGH, edge triggered) buffered parallel outputs terminal count output (active LOW)
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
January 1995
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Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
HEF4029B MSI
Fig.3 Logic diagram (continued in Fig.4).
January 1995
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Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
HEF4029B MSI
Fig.4 Logic diagram (continued from Fig.3).
January 1995
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Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
FUNCTION TABLE PL H L L L L L Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going clock pulse edge BIN/DEC X X L L H H UP/DN X X L H L H CE X H L L L L CP X X
HEF4029B MSI
MODE parallel load (Pn On) no change count-down, decade count-up, decade count-down, binary count-up, binary
Fig.5 State diagram; BIN/DEC = LOW.
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Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
HEF4029B MSI
Fig.6 State diagram; BIN/DEC = HIGH.
Logic equation for terminal count: TC = CE (BIN DEC * UP DN * O 0 * O 1 * O 2 * O 3 + BIN DEC * UP DN * O 0 * O 1 * O 2 * O 3 + BIN DEC * UP DN * O 0 * O 3 + BIN DEC * UP DN * O 0 * O 1 * O 2 * O 3 )
January 1995
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Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1000 fi + (foCL) x VDD2 4500 fi + (foCL) x VDD2 11 500 fi + (foCL) x VDD2 where
HEF4029B MSI
fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH CP TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH PL On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CE TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 145 55 40 160 60 40 280 105 70 195 75 55 120 50 35 170 65 45 180 70 50 170 65 50 290 110 75 315 120 80 560 205 140 385 150 105 240 100 70 335 130 90 360 140 100 335 135 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 118 ns + 44 ns + 32 ns + 133 ns + 49 ns + 32 ns + 253 ns + 94 ns + 62 ns + 168 ns + 64 ns + 47 ns + 93 ns + 39 ns + 27 ns + 143 ns + 54 ns + 37 ns + 153 ns + 59 ns + 42 ns + 143 ns + 54 ns + 42 ns + (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA
January 1995
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Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
VDD V Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL SYMBOL MIN. TYP. 60 30 20 60 30 20 MAX. 120 60 40 120 60 40 ns ns ns ns ns ns
HEF4029B MSI
TYPICAL EXTRAPOLATION FORMULA 10 ns + 9 ns + 6 ns + 10 ns + 9 ns + 6 ns + (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL
January 1995
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Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Minimum clock pulse width; LOW Minimum PL pulse width; HIGH Recovery time for PL Set-up times BIN/DEC CP 5 10 15 5 10 15 5 10 15 5 10 15 5 UP/DN CP 10 15 5 CE CP 10 15 5 Pn PL Hold times BIN/DEC CP 10 15 5 10 15 5 UP/DN CP 10 15 5 CE CP 10 15 5 Pn PL Maximum clock pulse frequency 10 15 5 10 15 fmax thold thold thold thold tsu tsu tsu tsu tRPL tWPLH tWCPL SYMBOL MIN 110 35 25 160 55 35 150 50 35 270 90 60 300 105 75 240 90 70 70 20 10 45 15 10 15 0 -5 30 10 5 15 0 0 2 5 8 TYP 55 20 15 80 25 15 75 25 20 135 45 30 150 55 35 120 50 40 35 10 5 -90 -30 -20 -135 -50 -35 -30 -10 -10 -20 -10 -5 4 10 15 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
HEF4029B MSI
see also waveforms Figs 7 and 8
January 1995
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Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
HEF4029B MSI
Fig.7
Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP, BIN/DEC to CP and UP/DN to CP. Set-up and hold times are shown as positive values but may be specified as negative values.
Fig.8
Waveforms showing minimum pulse width for PL, recovery time for PL, and set-up and hold times for Pn to PL. Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995
10
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Synchronous up/down counter, binary/decade counter HEF4029B MSI
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 12 Product specification Fig.10 Timing diagram; binary mode; P0 = HIGH; P1 = LOW; BIN/DEC = HIGH. Philips Semiconductors
Synchronous up/down counter, binary/decade counter HEF4029B MSI
Philips Semiconductors
Product specification
Synchronous up/down counter, binary/decade counter
APPLICATION INFORMATION Some examples of applications for the HEF4029B are: * Programmable binary and decade counting/frequency synthesizers - BCD output. * Analogue-to-digital and digital-to-analogue conversion. * Up/down binary counting. * Magnitude and sign generation. * Up/down decade counting. * Difference counting.
HEF4029B MSI
January 1995
13
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Note TC lines at all stages after the first may have a negative-going glitch pulse resulting from differential delays of different HEF4029B ICs. These negative-going glitches do not affect proper HEF4029B operation; however if the TC signals are used to trigger other edge-sensitive logic devices, such as flip-flops or counters, the TC signals should be gated with the clock signal using a 2-input OR gate such as HEF4071B.
Philips Semiconductors Product specification
Synchronous up/down counter, binary/decade counter HEF4029B MSI
Fig.12 Example of ripple clocking when cascading HEF4029B ICs. Ripple clocking mode: the up/down control can be changed at any count; the only restriction on changing the up/down control is that the clock input to the first counting stage must be HIGH.

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